Microelectronic devices usually include a large number of features or components—such as transistors, switches and conductive lines-built on an underlying substrate or wafer. The components are usually built by successively depositing layers of different materials on the substrate and then etching and/or selectively removing all or part of the deposited layers. The deposited layers are of different materials depending on the component, but can include metals, metal alloys, pure semiconductors, doped semiconductors, and dielectrics. Certain microelectronic devices include a variety of conducting paths or interconnects between components of the device. These interconnects are often built by etching a feature such as a trench, (i.e., a recess) into a dielectric layer, and then depositing a barrier layer and a conductive layer within the trench. To complete the interconnect, the conductive layer must be removed from the regions of the dielectric layer surrounding the feature (also known as the “field”), leaving the trench filled with the barrier layer and the conductive layer, usually metal, separated from the dielectric layer by the barrier layer.
The method of choice for removing the conductive and barrier layers from a semiconductor wafer has been chemical mechanical polishing (CMP). In CMP, a mildly abrasive slurry is poured onto a polishing pad, and the wafer surface is then pressed onto the slurry with a force calculated to exert a certain pressure on the surface of the wafer. The polishing pad and the surface of the wafer move against each other causing the abrasive slurry to grind away the conductive or barrier layers on the surface of the wafer.
One problem associated with the CMP process is that some areas of the substrate may exhibit a dishing 50 in the conductive layer after a CMP process has been performed (see FIG. 4a). This dishing 50 may be defined as the vertical distance from the top of a dielectric layer 40 to the bottom of a conductive layer 30 after the CMP process has been performed. The extent of the dishing 50 may be severe, in which the vertical distance from the top of the dielectric layer 40 to the bottom of the conductive layer 30 may be significant, or the extent of the dishing may be slight, and may include such things as scratches, abrasions, surface roughness, etc. Dishing refers to any sort of surface topography, such as mechanically induced topographic effects, such as pad bending, as is known in the art, but also to the chemically induced etching component often referred to as recessing, as is known in the art.
Dishing may lead to significant surface non-planarity in the conductive layer 30 which may cause various integration problems. For example, current processes tend to pass the topography of the dishing 50 from a lower conductive layer 30 to a higher conductive layer 32, which may cause hanging bumps 10 that can cause shorting between the various conductive layers (FIG. 4b). Prior art approaches to reduce or remove the amount of dishing 50 in the conductive layer 30 include removing some portion 22 of the dielectric layer 40 (see FIG. 4a) by using a CMP process which planarizes the conductive layer 30 and the dielectric layer 40, thus substantially removing the dishing 50. However, this approach cannot be performed when a hardmask layer 60 (a layer that stops the etching, or removal of an underlying layer) is used on the dielectric layer 40 without removing or damaging the hardmask layer 60 (see FIG. 4c).
Accordingly, there is a need for improved methods of removing the dishing in a conductive layer when a hardmask is used on a microelectronic device. The present invention provides such methods and their associated structures.